1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for manufacturing the same.
2. Description of the Related Art
Conventionally, a semiconductor memory device, such as a dynamic RAM, is constructed as shown in FIG. 1 and a gate electrode 1 of a select MOS transistor constitutes a word line of the memory cell.
At the time of a normal write operation, a voltage VCC+2VTH is applied to the word line 2 to turn the select MOS transistor ON. A bit "1" or "0" is written into a bit line 3. At a time of the read operation, the voltage VCC+2VTH is applied to the word line 2 to turn the select MOS transistor ON, reading out information from a capacitor 4 for information storage. It is to be noted that the increase in the voltage on the word line 2 is effected to increase a write or a read margin and to do so in an internal circuit.
The aforementioned conventional dynamic RAM has the following drawbacks.
When the voltage VTH on the select MOS transistor is, for example, 1.5 V, the voltage on the word line 2 becomes EQU 5 V(VCC)+(2.times.1.5 V)=8 V
When a gate oxide film 5 of the MOS transistor is, for example, 200 .ANG., it is less degenerated/destroyed under an electric field of 4 MV/cm applied to the gate electrode 1.
At a burn-in time in which the device is screened for initial defects, a test is made generally with a power supply voltage VCC raised. In the case of, for example, a 8 V power supply voltage VCC applied, a voltage on the word line 2 becomes 11 V and an electric field of 5.5 MV/cm is applied to the gate electrode 1 of the MOS transistor, causing degeneration and breakage of the gate oxide film 5. This leads to a lowered yield and lowered reliability.
If, against these drawbacks, the gate oxide film 5 is thickened so as to lower the electric field applied to the word line 2, the drive capability of the transistor at the peripheral circuit side is lowered, thus lowering an operation margin, such as the speed margin.